1. Field
Various features relate generally to apparatus comprising integrated circuit devices and more particularly to optimizing patterns of interconnects used to connect devices within the apparatus.
2. Background
In higher speed semiconductor integrated circuit (IC) devices, the layout and configuration of horizontal interconnects, which carry signals to and from ICs mounted on a circuit board or chip carrier, can play a critical role in signal integrity and can limit achievable maximum frequencies associated with the semiconductor device. Signaling rates continue to increase to obtain performance improvements in certain classes of high-speed semiconductor devices. In one example, the Joint Electron Device Engineering Council (JEDEC) standards for consecutive generations of synchronous dynamic random-access memory (SDRAM), including double data rate (DDR) SDRAM typically provide for increases in speed for later generations. One generation of Low Power DDR (LPDDR) SDRAM defined by JEDEC may provide for speeds that are double the speed of one or more preceding generations of LPDDR. Crosstalk between adjacent interconnects increases as signaling rates increase.
Conventionally, semiconductor designers employ intuitive insight in the design of horizontal interconnect patterns, configurations and assignments for coupling high-speed semiconductor devices. This design process is typically iterative and time-consuming, and often yields less than optimal results. Conventional methods for interconnect pattern optimization are not scalable and/or require a-priori knowledge. For instance, some prior art approaches focus on a very small problem size (up to 2 signals only) and cannot generally be scaled to larger interconnect patterns (e.g., to a full DDR interface design). Conventional approaches do not account for variable numbers of signal and power/ground interconnects and gaps that are available for placement between interconnects. In some conventional systems, a-priori knowledge is required including, for example, a-priori knowledge of an inductance matrix in an interconnect pattern when optimizing for simultaneous switching noise.
Therefore, a solution is needed that optimizes interconnect patterns for minimum crosstalk for an arbitrary number of signal and power/ground interconnects.